Registers; Register List - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

30.6 Registers

This section describes the SPI registers.

30.6.1 Register list

SPI is controlled by the following registers as shown in Table 30-1.
Table 30-1 SPI register list
Address
Base Offset
FFF4_0000 + 00 SPI 0 control register
H H
+ 04 SPI 0 slave control register
H
+ 08
H
SPI 0 data register
+ 0C SPI 0 status register
H
Address
Base Offset
FFF4_5000 + 00 SPI 1 control register
H H
+ 04 SPI 1 slave control register
H
+ 08
H
SPI 1 data register
+ 0C SPI 1 status register
H
30-4
Register Abbreviation
SPI0CR
SPI0SCR
SPI0DR
SPI0SR
Register Abbreviation
SPI1CR
SPI1SCR
SPI1DR
SPI1SR
Description
For general SPI settings
This sets SPI slave fixed setting
This writes and reads data to be
transmitted/received to SPI slave
This maintains SPI state
Description
For general SPI settings
This sets SPI slave fixed setting
This writes and reads data to be
transmitted/received to SPI slave
This maintains SPI state