Frame Construction; Sub Frame Construction - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

27.7.3 Frame construction

This module supports frame format of multiplexer channel construction. Frame is able to be set
to 1 or 2 sub frames; moreover, number of each frame's channel and word length are able to be
set individually.
27.7.3.1

1 sub frame construction

I2S_SCKx
1 bit Channel-length bit
I2S_WSx(FSLN=0)
I2S_WSx(FSLN=1) 0-1 bit
I2S_SDIx
I2S_SDOx
Description
1. When SBFN bit of CNTREG register is "0", frame becomes 1 sub frame composite.
2. Number of channel of 1 sub frame is determined by S0CHN of MC0REG register.
Up to 32 channels are settable.
3. Each channel bit length (word length) is determined by S0WDL of MC0REG register.
4. Sub frame channel starts from 0th, and each channel is settable to valid/invalid with the corresponding bit
of MC1REG register. Transmission/Reception of data is not performed to invalid channel.
5 Dummy bit can be inserted behind sub frame by setting OVHD of CNTREG register.
0-1023 bit are insertable.
6. Polarity of I2S_WSx is set with FSPL bit of CNTREG register.
7. Pulse width of I2S_WSx can be set to 1 bit or 1 word length by setting FSLN bit of CNTREG register.
8. Timing from the edge I2S_WSx becomes valid to the first bit of frame is settable to "0" or "1" bit.
In this construction, setting of S1CHN of MC0REG register, S1WDL register and MC2REG register are
9.
ignored.
Channel-0(7-32 bit) Channel-1(7-32 bit)
Figure 27-2 1 sub frame composite frame
Channel-n(7-32 bit)
One Sub frame(1-32 channels)
One Frame with one Sub frame
Over-Head
(0-1023 bit)
27-29