Register Access - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

3.2 Register Access

It is necessary to access MB86R02 'Jade-D' registers with word accesses (with the exception of a few
specific registers that are documented accordingly). Table 3-1 shows access data lengths for special
modules.
Table 3-1 Valid access data length of register
Module Register name
DMACR
DMAC
DMACA, DMACB, DMACSA,
DMACDA
UART RFR, TFR, DLL, DLM
GPIO PDR0, PDR1, PDR2
Others All registers other than the above
1
Little-endian addressing means:
- For byte access to a 32-bit register, bit[31:24] is at address offset 3, bit[23:16] at offset 2, bit[15:8] at
offset 1, bit[7:0] at offset 0.
- For half-word access to a 32-bit register, bit[31:16] is at address offset 2, bit[15:0] at offset 0.
3-4
Valid data length
Word (32 bit) / Half-word (16 bit) / Byte (8 bit)
For byte and half-word access, use little-endian
1
addressing .
Word (32 bit)/Half-word (16 bit)/Byte (8 bit).
For byte and half-word access, use little-endian
1
addressing .
Word(32 bit)/Byte(8 bit)
For byte access, use little-endian addressing.
Word(32 bit)/Byte(8 bit)
For byte access, use little-endian addressing
Word (32 bit)
1
1
.