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MB86R02 'Jade-D' Hardware Manual V1.64
5.1.8.
APB (A) bus clock gate control register (CRPA)
This register controls clock gate of APB (A) bus.
Address
Bit
31
30
29
Name
–
–
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
Bit
15
14
13
Name
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
1
1
1
Bit field
No.
Name
31-16
–
15-0
PAGATE[15:0] PACLK clock gate control
FFFE_7000
28
27
26
25
–
–
–
–
X
X
X
X
12
11
10
9
1
1
1
1
Unused bits.
Write access is ignored, and read value of these bits is undefined.
These bits control PACLK clock gate.
PAGATE[n]
0
PACLKn stops
1
PACLKn does not stop (initial value)
PACLK0: IRC
PACLK1: EXIRC
PACLK2: UART0, UART1
PACLK3: GPIO
PACLK4: RBC
PACLK5: 32 bit timer
PACLK6: I2C × 2 (I2C_0, I2C_1)
PACLK7: CAN × 2 (CAN_0, CAN_1)
PACLK8: UART2, UART3
PACLK9: ADC × 2 (ADC0, ADC1)
PACLK10: PWM0,1,2,3
PACLK11: SPI 0,1
PACLK12: CCNT
PACLK13: UART4, UART5
PACLK14: ETM9CSSingle APB port
PACLK15: (Reserved)
+ 1C
H
H
24
23
22
21
–
–
–
–
X
X
X
X
8
7
6
5
PAGATE[15:0]
1
1
1
1
Description
Description
20
19
18
17
–
–
–
–
X
X
X
X
4
3
2
1
1
1
1
1
5-29
16
–
X
0
1
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