Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
VCS (Video Capture Status)
Register address
Bit number
Bit field name
R/W
Initial value
This register indicates the ITU-RBT656 SAV and EAV status.
To detect error codes, set NTSC/PAL in the VS bit of VCM. If NTSC is set, reference the
number of data in the capture data count register (CDCN). If PAL is set, reference the
number of data in the capture data counter register (CDCP). If the reference data does not
match the stream data , or undefined Fourth word of SAV/EAV codes are detected, bits 4 to
0 of the video capture status register (VCS) will be values as follows.
Bits 6-0 CE0 (Capture Error 0)
Bit0
1 : RBT.656 undefined error (Code Bit7)
Bit1
1 : RBT.656 undefined error (Code Bit7-4)
Bit2
1 : RBT.656 undefined error (Code Bit7-0)
Bit3
1 : RBT.656 long term H code error (SAV)
Bit4
1 : RBT.656 long term H code error (EAV)
CaptureBaseAddress + 08h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserve
RX
X
0 : true
0 : true
0 : true
0 : true
0 : true
9
8
7
6
5
4
3
2
1
CE
RW0
00000
18-137
0
Advertisement
Table of Contents
