Spi Slave Control Register (Spinscr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

30.6.3 SPI slave control register (SPInSCR)

This register maintains unique setting of SPI slave.
All bits are cleared by moving state to sleep. Set this register at sleep or setup state.
Address
Bit 31 30 29
Name – – –
R/W R0 R0 R0
Initial value X X X
Bit 15 14 13
Name – – –
R/W R0 R0 R0
Initial value X X X
(Note) This register should be accessed in 32 bit unit.
Bit field
No. Name
31-29 –
28 SPE
27-25 –
24 DRVS
27-25 –
19-16 STL3-0
15-13 –
30-8
SPI0: FFF4_0000
SPI1: FFF4_5000
28 27 26 25
SPE – – –
R/W R0 R0 R0
0 X X X
12 11 10 9
DLN4 DLN3 DLN2 DLN1 DLN0
R/W R/W R/W R/W R/W
0 0 0 0
Unused bits.
The write access is ignored. The read value of these bits is always "0".
SPI's clock supply is controlled.
0 Clock supply to internal logic stops except certain part (initial value)
1 Clock is supplied to all the circuits
Write "1" to operate SPI. Its state changes from sleep to setup by setting SPE bit. It
changes to sleep by clear; at the same time, internal logic is reset except certain part.
Unused bits.
The write access is ignored. The read value of these bits is always "0".
Transfer order of serial data is specified.
0 MSB --> LSB (initial value)
1 LSB --> MSB
Unused bits.
The write access is ignored. The read value of these bits is always "0".
Strobe width is specified at pulse mode selection (SMOD = 1) in the range of SCK 1 ~
16 cycles.
0000 SCK 1cycle (initial value)
0001 SCK 2cycles
: :
1110 SCK 15cycles
1111 SCK 16cycles
Unused bits.
The write access is ignored. The read value of these bits is always "0".
+ 04
H H
+ 04
H H
24 23 22 21
DRVS – – –
R/W R0 R0 R0
0 X X X
8 7 6 5
– – SMOD SAUT
R0 R0 R/W R/W
0 X X 0
Description
20 19 18 17
– STL3 STL2 STL1 STL0
R0 R/W R/W R/W R/W
X 0 0 0
4 3 2 1
– – SSP1 SSP0
R0 R0 R/W R/W
0 X X 0
16
0
0
0