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MB86R02 'Jade-D' Hardware Manual V1.64
Document Change History
Version
Date
V1.64 (amended)
17.09.2013
V1.64
30.01.2013
V1.63
30.01.2012
V1.62
07.11.2011
V1.61
21.09.2011
V1.60
29.10.2010
V1.50
25.03.2010
Editor
Comment
RvReitzenstein
Table 'Pin Functional Description' rectified.
Amended row are marked with a change bar on the right side.
Amended entries are marked bold.
von Treuberg
Extended section 17.2.1.3 ' Jade-D Restrictions'.
Removed reference to Application note on APIX jitter (no
longer applies). Added hint on using Demand Mode for
DMA/UART transfers.
von Treuberg
Changed RSDS electrical characteristics.
von Treuberg
Changed Channel Mapping table (26.6).
von Treuberg
Corrected pin names in chapters 1, 7, 17:
APIX_n_SB > APIXn_SB_
APIX_SB0 > APIX0_SB
APIX_SB1 > APIX1_SB
APIX_SB5-0 > APIX0_SB
APIX1_SB5-0 > APIX1_SB
Modified section 5.1.13 (Only ES2 > Not available in ES1)
Extended Driving capability 2: list in 34.4.1, 3.3V Standard
CMOS I/O.
RLD: Changed statement 'little endian' to 'big endian'.
Removed 'Uplink' in description of CH0CFG/CH1CFG bits 6:3.
The swing setting has an effect regardless of RX/TX usage.
Corrected GPIO listings (number of GPIOs effected) with
concern to CMPX_MODE_10 descriptions in mulitplex
overview and register description.
Added an additional note concerning multiplex mode #3 if the
pins are unused (check the table for multiplex mode #3).
Corrected 9.6.1: address of instruction vector table to
0000_0080H.
Corrected IRQ connections diagram in chapter 9. IRQ5 is
connected to IRC2.
Added information about unused case for TRACEDATA_X
pins in pinmultiplex mode #3.
Replaced MediaLB Signal Timings chapter.
von Treuberg
Added new section in Electrical Characteristics: 'Transmitter
Serial Data Signal Characteristics'
von Treuberg
SSCG: Modified modulation peak values (e.g. 3% > 2x 1.56%),
added SSCG settings table for recommended value of 20 kHz.
CRG: Modified table 5-1 Clock Overview List
Electrical Characteristics: Added important requirement for
APIX PLL stability (power-on procedure)
EXTBUS: 11.6.1 corrected typo in description for NOR flash
page access mode.
CNT: Corrected reset values of register CAXI_PS and
CMUX_MD.
EXTBUS: modified diagram in section 11.8 (Word write access
to 16 bit width SRAM/NOR Flash)
I2S: corrected FIFO size from previously documented 18/36
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