Ocd Adjustment Procedure - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
13.7.2.2

OCD Adjustment Procedure

The figure below is the OCD adjustment setting procedure of SSTL_18 IO used for the DDR2
SDRSAM interface. The setting adjusts driver output impedance of SSTL_18 IO to the optimum
value. The pin for OCD adjustment is MDQ[31:0], MDM[3:0], MDQS[3:0], and MDQSN[3:0],
however, only MDQ[0] is tested for adjustment.
Write "0000" to DRIBSODT1 register (offset + 64h)
Write "001B" to DRIBSOCD register (offset + 66h)
Write "0001" to DRIBSOCD2 register (offset + 68h)
Write "0081" to DROABA register (offset + 70h)
Write "0F0F ~ 0000" to DROISR1 register (offset + 98h)
Write "0F0F ~ 0000" to DROISR2 register (offset + 9Ah)
Read DRIMR1 register (offset+90h)
Read DRIMR2 register (offset + 92h)
Read DRIMR3 register (offset + 94h)
Read DRIMR4 register (offset + 96h)
Write "0017" to DRIBSOCD register (offset + 66h)
Write "0X0X ~ FXFX" to DROISR1 register (offset + 98h)
Write "0X0X ~ FXFX" to DROISR2 register (offset + 9Ah)
Read DRIMR1 register (offset + 90h)
Judge (DRIMR1.DQX[0] = "0")
Write "0000" to DRIBSODT1 register (offset + 64h)
Write "0000" to DRIBSOCD register (offset + 66h)
Write "0000" to DRIBSOCD2 register (offset + 68h)
START
Judge (DRIMR1-4 = all "1")
END
OCD adjustment mode on
Set to driver PMOS adjustment mode
Decrement PMOS driver setting value
which is corresponding to the change of
DRIMR 1.DQX[0] from "0" to "1"
DRVP1/2/3/4 = Decrement to 0 ~ F
DRVN1/2/3/4 = 0
Read adjustment level of PMOS driver output
impedance from DRIMR1 register
(x=1..4) must have the same
All DRVNx
value.
Set to driver NMOS adjustment
Increment applied NMOS driver setting value
until DRIMR1.DQX[0] register changes from
"0" to "1"
DRVP1/2/3/4 = Retain
DRVN1/2/3/4 = Increment to 0 ~ F
Read adjustment level of NMOS driver
output impedance from DRIMR1 register
For DRVN1/2/3/4 and DRIMR1/2/3/4 registers,
refer Table 13-5 and Table 13-6
OCD adjustment mode off
Set to normal driver mode
13-33