Spi Data Register (Spindr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

30.6.4 SPI data register (SPInDR)

This register is used to write/read data to be transmitted to/received from SPI slave.
Address
Bit 31 30 29
Name D31 D30 D29
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0
Bit 15 14 13
Name D15 D14 D13
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0
(Note) This register should be accessed in 32 bit unit.
Do not operate this register in the busy state.
Bit field
No. Name
31-0 D31-0
SPI0: FFF4_0000
SPI1: FFF4_5000
28 27 26 25
D28 D27 D26 D25 D24
0 0 0 0
12 11 10 9
D12 D11 D10 D9
0 0 0 0
Transmission/Reception data to SPI slave is stored.
SPIDR is reset at moving to the sleep state. Writing to this register in the setup state
starts transmission/reception of the data length specified in DLN[4:0] bit of SPI slave
control register (SPISCR), and LSB is fixed regardless of the data length.
+ 08
H H
+ 08
H H
24 23 22 21
D23 D22 D21 D20 D19
0 0 0 0
8 7 6 5
D8 D7 D6 D5
0 0 0 0
Description
20 19 18 17
D18 D17 D16
0 0 0 0
4 3 2 1
D4 D3 D2 D1
0 0 0 0
30-11
16
0
0
D0
0