Increment And Lap Transfer - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

Increment and lap transfer

When increment beat transfer (INCR, INCR4, INCR8 and INCR16) or lap beat transfer (WRAP4,

WRAP8, and WRAP16) are set to DMACA/BT, sequential source access and destination access

are executed using the DMAC's 64 byte FIFO.

In the case of INCR4 (DMACA/BT = 4'b1011), the DMAC performs 4 sequential source accesses.

Output data from the source is stored in the DMAC's FIFO, then the data is sequentially driven to

the destination.

DMACA[19:16]

Figure 15-8 Increment/Lap beat transfer (example of INCR4 block transfer)

SA SA SA DA DA