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MB86R02 'Jade-D' Hardware Manual V1.64
DCM3 (Display Control Mode 3)
DisplayBaseAddress + 0x108
Register address
31
28 27 26 25 24 23 22 21 20 19 18 17 16 15-13 12 11 10 9
Bit number
Bit field name
reserved
R0W0
R/W
0000
Initial value
Bit4-0
DCKD (Display Clock Delay)
This defines additional delay time by internal PLL clock period.
00000
00010
00100
00110
:
11110
xxxxx1
Bit8
DCKinv (Display Clock inversion)
0:
1:
Bit9
DCKed (Display clock edge)
This defines which edge mode is used.
0:
1:
Bit10
POM (Parallel output Mode)
This defines a way to output two data streams for two display
0:
1:
Bit12
RSDS clock generation
This defines clock generation for DPERI and TCON module
0:
1:
2
Only use with TCON in bypass
3
This setting is needed if TCON is active (for both modes RSDS and TTL)
4
This value is set as default for ES1.
18-70
RW
RW
0
0
0
0
0
0
0
2
No additional delay
+1 PLL clock
+2 PLL clocks
+3 PLL clocks
:
+15 PLL clocks
all reserved
DCLKO output signal is not inverted
DCLKO output signal is inverted.
2
single edge mode in which positive edge is used for digital RGB output.
bi-edge mode in which positive edge and negative edge are used for digital RGB
output to identify two data streams.
multiplex output mode in which two data streams are multiplexed and goes to the
digital RGB output.
parallel output mode in which one data stream go to the digital RGB output and
another data stream goes to the analog RGB output.
No RSDS bit clock generation, clock is output 1:1
RSDS bit clock generation active (RSDS bit clock is 2x pixel clock)
reserved
RW0
R0W0
0
0
0
0 1
0
0
2
8
7-5
4
DCKD
RW
R0W0
RW
0 0
0
0
000
00000
3 4
0
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