Soft Reset Register (Csrst) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

7.4.3 Soft reset register (CSRST)

Address
Bit 31 30 29
Name (Reserve)
R/W R R R
Initial value 0 0 0
Bit 15 14 13
Name (Reserve)
R/W R R R
Initial value 0 0 0
Bit field
Number Name
31-1 (Reserved)
0 SFTRST
(Soft Reset)
ix_PRESETn
i_TEST
7-6
FFF4_2000 + 04h
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
R R R R
0 0 0 0
Reserved
Writes are ignored. Reads will return a '0' at all times.
Reset this unit by writing "1" to this bit.
The various units: GDC, DDR2, CAN, SDMC, MediaLB, I2S, SPI, I2C, PWM, UART, GPIO,
and HDMAC are reset.
The value of this bit should be set to "0" again at reset release.
0 No Reset (initial value)
1 Reset
Jade Control
Macro
Soft
Reset
Register
Soft
Reset
Register
Figure 7-1 Details of Soft Reset
24 23 22 21
R R R R
0 0 0 0
8 7 6 5
R R R R
0 0 0 0
Function
0
1
0
1
20 19 18 17
R R R R
0 0 0 0
4 3 2 1
R R R R
0 0 0 0
ox_RST0
ox_RST1
0
ox_RST31
1
16
R
0
0
SFTRST
R/W
0