Timing Controller (Tcon); Position Of Block In Whole Lsi; Overview; Feature List - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

22 Timing Controller (TCON)

The Timing Controller module TCON allows the generation of control signals and data signals for

direct interfacing to the column and row drivers of a display panel. The freely programmable waveform

of the generated timing control signals allows the emulation of almost every timing controller IC

(TCON IC) commonly used in display panels. The RGB data is transmitted as single-ended TTL

signals or as low voltage differential swing signals conforming to the RSDS™ standard (Reduced

Swing Differential Signal).

The module consists of three submodules; a Timing Signal Generator (TSIG) module, an RSDS™ bit

mapping module (RBM) and an IO module for control of special RSDS™ or TTL capable IO-cells. The

TSIG IP is derived from Fujitsu's MB87P2020 (Jasmine) SyncSig IP (please refer to the MB87P2020

Hardware Manual).

RBM (RSDS Bit Mapping)

Conforms to RSDS™ Standard 1.0 (National Semiconductors)

Support for single bus (Multidrop bus with single or double end termination)

Mapping for 6 bit color depth

Mapping for 8 bit color depth

Data and clock outputs can flexible be assigned to the pool of available pins to ease board

RSDS™ "Intra-Panel" Interface Specification, Revision 1.0, May 2003, (National Semiconductor

Corporation©)

Figure 22-1 Location of the TCON in the GDC