Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
13.6.9 DRAM CTRL REFRESH register (DRCR)
This register sets auto. refresh occurrence interval to DRAM. After changing this register value,
refresh occurs irregularly.
Address
Bit
15
14
13
Name
-
-
-
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
Bit field
No.
Name
15-9
(Reserved)
8
CNTLD
7-0
REF_CNT
13-14
F300_0000
12
11
10
9
-
-
-
-
X
X
X
X
Reserved bits.
Write access is ignored.
Counter load.
REF_CNT value is forcibly loaded into internal counter.
When this bit is set to 0 → 1, REF_CNT value of bit[7:0] is forcibly loaded into internal
refresh counter.
This is used when setting value needs to be applied, such as after REF_CNT value
change. This bit does not need to be rewritten to 0 immediately after loaded because
it is performed after detecting the bit change. However, this bit keeps the writing
value. If bit value is not 0 at executing load operation, "1" should be written after
writing "0".
Although CNTLD is not used after REF_CNT change, it operates with the changed
REF_CNT by having the period before setting REF_CNT.
Refresh count.
Auto. refresh request occurrence is set in 16 cycle.
Refresh request is continuously issued. Priority of refresh is higher
00
than the read/write. Although access request to DRAM occurs, only
H
refresh occurs with this setting.
Refresh request occurs in REF_CNT × 16 clock interval. If DRAM
01
- FF
data is accessed at refresh request, refresh does not start until the
H
H
access is completed.
+ 0E
H
H
8
7
6
5
CNTLD
0
0
0
0
Description
4
3
2
1
REF_CNT
R/W
0
0
0
0
0
0
Advertisement
Table of Contents
