Initram Control Register A (Rbitra) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
8.5.4

INITRAM control register A (RBITRA)

The INITRAM control register A (RBITRA) controls the INITRAM output signal.
This register is reset by the CRSTn input. It should be accessed in word accesses.
Address
Bit 31 30 29
Name
R/W R R R
Initial value 0 0 0
Bit 15 14 13
Name
R/W R R R
Initial value 0 0 0
Bit field
No. Name
31-1 (Reserved)
0 ITRA
8-6
GPR0: FFFE_6000
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
R R R R
0 0 0 0
Reserved bits.
Write access is ignored. Read value of these bits is always "0".
INTRAM output signal is controlled.
+ 0C
H H
24 23 22 21
(Reserved)
R R R R
0 0 0 0
8 7 6 5
(Reserved)
R R R R
0 0 0 0
Description
20 19 18 17
R R R R
0 0 0 0
4 3 2 1
ITRA
R R R R R/W
0 0 0 0
16
R
0
0
0