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MB86R02 'Jade-D' Hardware Manual V1.64
7.4.18 Soft reset register 0 for macro (CMSR0)
Address
Bit
31
30
29
Name
(Reserved)
R/W
R/W
R/W
R/W
Initial value 0
0
0
Bit
15
14
13
Name
(Reserved)
R/W
R/W
R/W
R/W
Initial value 0
0
0
Bit field
Number
Name
31-26
(Reserved)
25
SRST0_25 (UART1
Soft Reset)
24
SRST0_24 (UART0
Soft Reset)
23-17
(Reserved)
16
SRST0_16 (HDMAC
Soft Reset)
15-8
(Reserved)
7
SRST0_7 (GPIO Soft
Reset)
6
(Reserved)
5
SRST0_5 (???)
7-28
FFF4_2000 + F0h
28
27
26
25
SRST0_25 SRST0_24 (Reserved)
R/W
R/W
R/W
R/W
0
0
0
0
12
11
10
9
R/W
R/W
R/W
R/W
0
0
0
0
Reserved
Writes are ignored. Reads will return a '0' at all times.
Reset the UART1 macro by writing "1" to this bit.
Set a '0' in this bit(field) during reset release.
0
No Soft Reset (initial value)
1
Soft Reset
Reset the UART0 macro by writing "1" to this bit.
Set a '0' in this bit(field) during reset release.
0
No Soft Reset (initial value)
1
Soft Reset
Reserved
Writes are ignored. Reads will return a '0' at all times.
Reset the HDMAC macro by writing "1" to this bit.
Set a '0' in this bit(field) during reset release.
0
No Soft Reset (initial value)
1
Soft Reset
Reserved
Writes are ignored. Reads will return a '0' at all times.
Reset the GPIO macro by writing "1" to this bit.
Set a '0' in this bit(field) during reset release.
0
No Soft Reset (initial value)
1
Soft Reset
Reserved
Writes are ignored. Reads will return a '0' at all times.
???
24
23
22
21
R/W
R/W
R/W
R/W
0
0
0
0
8
7
6
5
SRST0_7 (Reserved) SRST0_5 SRST0_4 SRST0_3 SRST0_2 SRST0_1 SRST0_0
R/W
R/W
R/W
R/W
0
0
0
0
Function
20
19
18
17
R/W
R/W
R/W
R/W
0
0
0
0
4
3
2
1
R/W
R/W
R/W
R/W
0
0
0
0
16
SRST0_16
R/W
0
0
R/W
0
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