Drawing Control Registers - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
18.11.5

Drawing control registers

CTR (Control Register)
Register
DrawBaseAddress + 400
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
Initial value
This register indicates drawing flags and status information. Bits 24 to 22 are not cleared until 0 is set.
Bit 1 and 0 PS (Pixel engine Status)
Indicate status of pixel engine unit
00
01
10
11
Bit 5 and 4 DS (DDA Status)
Indicate status of DDA
00
01
10
11
Bit 9 and 8 SS (Setup Status)
Indicate status of Setup unit
00
01
10
11
Bit 12 FE (FIFO Empty)
Indicates whether data contained or not in display list FIFO
0
1
Bit 13 FF (FIFO Full)
Indicates whether display list FIFO is full or not
0
1
Bit 14 NF (FIFO Near Full)
Indicates how empty the display list FIFO is
H
FO CE
RW RW
0 0
Idle
Busy
Reserved
Reserved
Idle
Busy
Busy
Reserved
Idle
Busy
Reserved
Reserved
Valid data
No valid data
Not full
Full
FCNT
NF FF FE
R R R R
011101 0 0 1
SS DS PS
R R R
00 00 00
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