Transition State - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

30.5 Transition state

Figure 30-3 shows SPI transition state chart.

Detail of each state shown in Figure 30-3 is as follows. SPI moves to reset state with hardware

reset (HRESETn = 0) from all conditions (broken line in the chart.)

Sleep (SLEEP)

Initial state of SPI.

Clock is not supplied except to state machine. While setup or transition from error state,

internal logic is initialized except certain part.

Setup (SETUP)

Stand-by state of communication between master and slave. SPI changes state in the

following cases.

Received data should be read in the setup state.

Communicating state with SPI slave.

Writing SPI data register (SPIDR) in the setup state moves to this state; in that time,

transmission/reception of the data are performed simultaneously. When 1 bit is output

to SPI_DO pin, 1 bit is input from SPI_DI pin.

Set SIRQ at the normal termination of the communication.

Error (ERROR)

Performing prohibited register access in the busy state moves to this state. Clearing

SPE bit of SPI slave control register (SPISCR) returns to sleep (SLEEP) state.

Figure 30-3 SPI state transition chart

SPE bit of SPI slave control register (SPISCR) is set to "1" in the sleep state

Communication completes properly in the busy state