Fujitsu MB86R02 Jade-D Hardware Manual page 752

MB86R02 'Jade-D' Hardware Manual V1.64
Reception only mode
Transfer Operation
setting
Reception Start
only
TXDIS = 1
RXDIS = 0
Stop
Abnormality When writing to reception FIFO occurs
Note:
1. TXDIS and RXDIS are for setting to enable and disable transmission/reception of CNTREG register.
2. start, TXENB, and RXENB are operation control bits of OPRREG register.
Master mode (MSMD = 1)
Free-running mode (FRUN = 1):
Frame synchronous signal starts to
output after start bit becomes "1" and
TXENB bit is "1" when transmission
FIFO is not empty.
From the 2nd time, output frame
synchronous signal with the frame rate
determined by the register setting.
Burst mode (FRUN = 0):
When start bit is "1" and RXENB bit is
"1", output frame synchronous signal to
receive frame if reception FIFO is not
full. If the FIFO is full, the signal does
not output.
At the time of stop, frame is not
imported from serial bus even though
reception FIFO is empty in the
condition that data transfer from I2S
reception FIFO to internal memory is
not required.
To maintain start bit to "1"
Write "0" to RXENB and empty
reception FIFO.
Although frame synchronous signal is
kept outputting in the free-running
mode, frame is not received. In the
burst mode, frame is not received and
the signal is not output.
To make start bit "0"
Write "0" to start bit, then reception
FIFO becomes empty. Clock supply to
the serial control part stops regardless
of RXENB setting, and I2S_SCKx
supply to the external part is stop as
well.
with having it full, set RXOVR to "1".
The bit also should be set to "1" when
read access to reception FIFO occurs
with having it empty.
Slave mode (MSMD = 0)
Free-running mode (FRUN = 1):
When start bit is "1" and RXENB bit is
"1", input frame synchronous signal
with the frame rate determined by the
register setting. Frame should be
received every time the signal is input.
Burst mode (FRUN = 0):
When start bit is "1" and RXENB bit is
"1", perform frame reception every time
frame synchronous signal is input.
The signal is input with less speed than
the frame rate in the free-running mode.
To maintain start bit to "1"
Reception FIFO becomes empty by "0"
writing to RXENB.
Ignore the input frame synchronous
signal, and do not receive the frame.
To make the start bit "0"
Write "0" to the start bit, then reception
FIFO becomes empty.
Ignore the input frame synchronous
signal regardless of RXENB setting,
and do not receive the frame.
When writing to reception FIFO occurs
with having it full, set RXOVR of the
STATUS register to "1". When read
access to reception FIFO occurs with
having it empty, set RXUDR of the
register to "1".
Free-running mode:
If frame synchronous signal is not input
with the frame rate defined by the
register setting, set FERR bit of the
register to "1".
Burst mode:
Set the bit also to "1" if the next frame
synchronous signal is input during 1
frame reception.
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