Fujitsu MB86R02 Jade-D Hardware Manual page 100

MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
No. Name
4-0 PLLMODE[4:0] PLL oscillation mode
5-20
These bits are used to set PLL oscillation mode.
Initial value of PLLMODE[4:0] bit changes according to the setting of external pin,
CRIPM[3:0]. Initial value of these bits is PLLMODE[4:0] = {"0", CRIPM[3], CRIPM[2],
CRIPM[1], CRIPM[0].}
× 10.67 (64 x 1/3 × 1/2)
00000 f = f
CCLK CLK
× 13.33 (80 x 1/3 × 1/2)
00001 f = f
CCLK CLK
× 16.00 (32 × 1/2)
00010 f = f
CCLK CLK
× 16.50 (33 × 1/2)
00011 f = f
CCLK CLK
× 10.17 (61 x 1/3 × 1/2)
00100 f = f
CCLK CLK
× 12.75 (51 x 1/2 × 1/2)
00101 f
= f
CCLK CLK
× 15.33 (92 x 1/3 × 1/2)
00110 f
= f
CCLK CLK
00111 reserved
× 8.5 (17 × 1/2)
01000 f = f
CCLK CLK
01001 reserved
01010 reserved
01011 reserved
11111 PLL stops
Others Reserved (setting prohibited)
f : Clock frequency of CCLK
CCLK
f : Clock frequency of external pin CLK
CLK
Note: Do not change PLLMODE[4:0] when PLLBYPASS bit is 0.
Description