Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
24.6.2 Port data register 0-2 (GPDR0-2)
Registers GPDR0 - 2 are to set in order to input/output data on the GPIO port. Their
corresponding GPIO pin assignments are as follows:
• GPDR0: GPIO bit 7 - 0 (GPIO_PD[7:0] pin)
• GPDR1: GPIO bit 15 - 8 (GPIO_PD[15:8] pin)
• GPDR2: GPIO bit 23 - 16 (GPIO_PD[23:16] pin)
The input/output direction of data for each GPIO unit is determined by the corresponding bit in
the GPDDR0 - 2 registers.
Address
Bit
31
30
29
Name
R/W
–
–
Initial value
X
X
X
Bit
15
14
13
Name
R/W
–
–
Initial value
X
X
X
Bit field
No.
Name
31-8
(Reserved)
7-0
PDR0_7-0
GPDR0: FFFE_9000
GPDR1: FFFE_9000
GPDR2: FFFE_9000
28
27
26
25
–
–
–
–
X
X
X
X
12
11
10
(Reserved)
–
–
–
–
X
X
X
X
Reserved bits.
Write access is ignored. Read value of these bits is undefined.
GPDR0 register's bit field.
The register is setting register of GPIO_PD[7:0] pin's input/output data, and each bit
corresponds to a GPIO pin as follows.
•
PDR0_7: GPIO_PD[7] pin
•
PDR0_6: GPIO_PD[6] pin
•
PDR0_5: GPIO_PD[5] pin
•
PDR0_4: GPIO_PD[4] pin
•
PDR0_3: GPIO_PD[3] pin
•
PDR0_2: GPIO_PD[2] pin
•
PDR0_1: GPIO_PD[1] pin
•
PDR0_0: GPIO_PD[0] pin
Input/Output directions of GPIO_PD[7] ~ GPIO_PD[0] pins are determined by the
corresponding bit of GPDDR0 register.
Initial value of these bits is undefined.
+ 00
H
H
+ 04
H
H
+ 08
H
H
24
23
22
21
(Reserved)
–
–
–
–
X
X
X
X
9
8
7
6
PDR0_7
PDR0_6
PDR0_5
PDR1_1
PDR1_1
PDR1_1
5
4
PDR2_2
PDR2_2
PDR2_2
3
2
–
–
R/W R/W R/W R/W R/W R/W R/W R/W
X
X
X
X
Description
20
19
18
17
–
–
–
–
X
X
X
5
4
3
2
PDR0_4
PDR0_3
PDR0_2
PDR0_1
PDR1_1
PDR1_1
PDR1_1
PDR1_9
3
2
1
0
PDR2_1
PDR2_2
PDR2_1
PDR2_1
1
0
9
8
X
X
X
16
–
–
X
X
1
0
PDR0_0
PDR1_8
PDR2_1
7
6
X
X
24-5
Advertisement
Table of Contents
