Fujitsu MB86R02 Jade-D Hardware Manual page 98

MB86R02 'Jade-D' Hardware Manual V1.64
5.1.2. PLL control register (CRPR)
This register controls the main PLL.
Address
Bit 31 30 29
PLLD
Name
EN
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0
Bit 15 14 13
Name
R/W R0 R0 R0
Initial value 0 0 0
*1: PLLBYPASS
*2: This follows external pin, PLLBYPASS
*3: This changes according to setting value of external pin, CRIPM[3:0] and PLLBYPASS
Bit field
No. Name
31 PLLDEN
30-24 PLLNDIV[6:0]
23 Reserved
22-18 –
17-16 PLLPDIV[1:0]
15-9 (Reserved)
5-18
FFFE_7000
28 27 26 25
PLLNDIV
0 0 1 1
12 11 10 9
(Reserved)
R0 R0 R0 R0
0 0 0 0
PLL feedback and pre divider direct control enable
0 Disabled (initial value), Register PLLMODE is effective
Enabled, Register PLLMODE has no effect, Register PLLPDIV and PLLNDIV
1
are active
Note: Do not change PLLDEN bit during PLLBYPASS bit is 0
PLL feedback divider value
Has only effect if PLLDEN=1b.
PLLNDIV[6:0] = NDIV, allowed range: 6(decimal)..96(decimal),
Only values for which 250MHz < f
PLLNDIV × ½
Note: Only change PLLNDIV bits during PLLDEN=0
Reserved bit.
Unused bits.
Write access is ignored, and read value of these bits is undefined.
PLL Pre dividing mode
Has only effect if PLLDEN=1b.
These bits set frequency dividing ratio of PLL input clock. ].
× (1/1) (initial value)
00 F = f
PLLIN OSCCLK
× (1/2)
01
F = f
PLLIN OSCCLK
× (1/3)
10 F = f
PLLIN OSCCLK
× (1/4)
11 F = f
PLLIN OSCCLK
Note: Only change PLLPDIV bits during PLLDEN=0
Reserved bits.
Write access is ignored, and read value of these bits is always "0".
+ 00
H H
24 23 22 21
reser
– –
ved
R R/W R/W R/W R/W R/W R/W R/W
0 X X X
8 7 6 5
PLLRDY *1 LUWMODE[1:0]
R R/W R/W R/W R/W R/W R/W R/W R/W
0 0 *2 1 0
Description
< 333MHz is valid are allowed. f
CCLK
20 19 18 17
– – – PLLPDIV
X X X 0
4 3 2 1
PLLMODE[4:0]
1 *3 1 *3 1 *3 1 *3
= f
CCLK CLK
16
0
0
1 *3
×