Burst Transfer - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

Burst transfer

In burst transfer mode, DMA transfer is executed for a number of blocks, multiplied by the

number of transfers (DMACA/BC × DMACA/TC) using 1 request.

When the number of transfers (DMACA/TC) is set to values other than "0", TC is decremented by

1 after completing the DMA transfer. DMA transfer is completed after the last transfer (BC is 4'h0

and TC is 16'h0000).

Transfer gap

After completing DMA transfer, DMAC negates the bus request to the arbiter so that a transfer

gap does not occur in burst transfer mode.

completing DMA transfer.

Transfer request

Software request, external (DREQ), and peripheral (IDREQ) requests are valid in this mode.

• Software request

Set "1" to DMACA/ST and set 5'b00000 to DMACA/IS

• External request

Set "0" to DMACA/ST and set 5'b01110 (rising edge of transfer request) or 5'b01111 (falling

edge of transfer request) to DMACA/IS

• Peripheral request

Set "0" to DMACA/ST and set 5'b1**** (rising edge of transfer request) to DMACA/IS

When external request or peripheral request mode is selected, the DMAC detects the transfer

request edge. When DMA transfer of BC × TC is executed by either of these requests, the DMAC

is unable to detect the next transfer; however it is able to detect the next transfer request after

DMA transfer of BC × TC has been completed.