Operation; Operation Procedure; Instruction For Use - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

10.6 Operation

External interrupt controller issues request signal to interrupt controller (IRC0) when input request

level of external interrupt is input to corresponding channel after setting EIENB and EILVL

If interrupt from this module is higher than interrupt level set in ILM register and it is highest priority

as a result of interrupt prioritization occurred in IRQ level decision circuit, IRQ interrupt request is

issued to ARM core.

From external pins

External interrupt register setting procedure is as followings.

1. Disable EIENB register related bit

2. Set EILVL register related bit

3. Clear EIREQ register related bit

4. Enable EIENB register related bit

EIENB register must be disabled to set register in the module; moreover, EIREQ register needs to

be cleared before EIENB register is enabled. This operation is to prevent accident caused by

incidental interrupt source during register setting.

This section indicates notice for using external interrupt.

Notice for returning from Stop mode

When external interrupt is used to return from Stop mode, where clock is stopped, set input

request level to "H" since "L" level request may cause malfunction. Moreover, the edge request

is not able to return from the Stop mode.

IRC0 (Interrupt Controller 0)

Figure 10-2 Operation of external interrupt

Compare interrupt level