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MB86R02 'Jade-D' Hardware Manual V1.64
27.6.9 I2SxOPRREG register
Address
Bit
31
30
29
Name
R/W
R
R
R
Initial
0
0
0
Bit
15
14
13
Name
R/W
R
R
R
Initial
0
0
0
Bit field
No.
Name
31-25
(Reserved)
24
RXENB
23-17
(Reserved)
16
TXENB
15-1
(Reserved)
0
start
27-14
ch0：FFEE_0018 (h)
28
27
26
25
(Reserved)
R
R
R
R
0
0
0
0
12
11
10
9
R
R
R
R
0
0
0
0
Reserved bits.
The write access is ignored. The read value of these bits is always "0".
Enable/Disable functions of receiving operation is set.
0 Receiving operation is disabled
Reception FIFO becomes empty with writing "0" to this bit
When RXENB is "0", the data received from serial reception bus is not
written to reception FIFO
DMA reception channel stops during DMA transfer
1 Receiving operation is enabled
Reserved bits.
The write access is ignored. The read value of these bits is always "0".
Enable/Disable functions of transmitting operation is set.
0 Transmitting operation is disabled
Reception FIFO becomes empty with writing "0" to this bit
When TXENB is "0", the data written to TXFDAT register from CPU or
DMA is not written to transmission FIFO
DMA reception channel stops during DMA transfer
1 Transmitting operation is enabled
Reserved bits.
The write access is ignored. The read value of these bits is always "0".
I2S is enabled/disabled.
0 I2S is stop, and internal transmission/reception FIFO becomes empty by
writing "0" to this bit
1 I2S is operable
Prohibit overwriting CNTREG, MCR0REG, MCR1REG, and MCR2REG registers when
Start is "1".
24
23
22
21
RXEN
B
R/W
R
R
R
0
0
0
0
8
7
6
5
(Reserved)
R
R
R
R
0
0
0
0
Description
20
19
18
17
(Reserved)
R
R
R
R
0
0
0
0
4
3
2
1
R
R
R
R
0
0
0
0
16
TXENB
R/W
0
0
start
R/W
0
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