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MB86R02 'Jade-D' Hardware Manual V1.64
Bit 4-0: CS4-0 (Clock Period Select 4-0)
This bit is used to set the frequency of the serial transfer clock.
The upper limit of the bus clock frequency can be extended using the I2CxECSR register. Refer to
"29.7.8 Expansion CS register (I2CxECSR)" for details.
If the I2CxECSR register is not used (the I2CxECSR register is used in its initial state), the
frequency (fscl) of the serial transfer clock is calculated using the expression shown below.
Standard mode
High-speed mode
fscl
Be sure to set fscl so that it doesn't exceed the following values during master operation.
• Standard mode: 100KHz.
• High-speed mode: 400KHz.
The APB clock φ of this module should be used within the range shown below.
If it is less than the range, transmission at the max. transfer rate is not guaranteed.
If it exceeds the range, the upper limit of the bus clock frequency can be extended by setting the
I2CxECSR register.
• Master operation: 14MHz ~ 18MHz.
• Slave operation: 14MHz ~ 18MHz.
• During register access operation: 14MHz ~ 41.5MHz
Note:
+2 cycle is the min. overhead for detecting the output level change of the SCL line. If
the rising edge delay of the SCL line is large or the clock is expanded for the slave
device, the value is larger than the value stated above.
The value of m to CS4 ~ 0 is shown in the next page
φ
=
fscl
2 (
×
)
+
2
m
φ
=
int(
1
5 .
×
)
+
2
m
φ
:
APB
φ
_
:
APB
clock
int(
: )
Round
off
after
_
clock
decimal
poin
t
29-13
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