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MB86R02 'Jade-D' Hardware Manual V1.64
10.5.4 External interrupt level register (EILVL)
This register is to select input request level detection.
Address
Bit
31
30
29
Name
–
–
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
Bit
15
14
13
Name
–
–
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
Bit field
No.
Name
31-8
–
7-0 LVL3[1:0] - LVL0[1:0]
FFFE_4000
28
27
26
25
–
–
–
–
X
X
X
X
12
11
10
9
–
–
–
–
X
X
X
X
Unused bit.
Write access is ignored. Read value of these bits is undefined.
Input request level detection of external interrupt is selected.
2 bit is allocated to each external interrupt channel. This is initialized to "01
reset.
LVL0[1:0]: External interrupt 0 (INT_A[0] pin)
LVL1[1:0]: External interrupt 1 (INT_A[1] pin)
LVL2[1:0]: External interrupt 2 (INT_A[2] pin)
LVL3[1:0]: External interrupt 3 (INT_A[3] pin)
LVL3-0[1]
LVL3-0[0]
0
0
0
1
1
0
1
1
+ 08
H
H
24
23
22
21
–
–
–
–
X
X
X
X
8
7
6
5
–
LVL3[1] LVL3[0] LVL2[1] LVL2[0] LVL1[1] LVL1[0] LVL0[1] LVL0[0]
X
0
1
0
Description
Input request level
"L" Level
"H" Level
Rising edge
Falling edge
20
19
18
17
–
–
–
–
X
X
X
X
4
3
2
1
1
0
1
0
" by
B
10-7
16
–
X
0
1
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