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MB86R02 'Jade-D' Hardware Manual V1.64
22.5.2.4
Timing Signal Module (TSIG) .............................................................................. 22-32
22.5.2.5
Inversion Signal Generation ................................................................................ 22-37
22.5.2.6
Bypass-Mode ....................................................................................................... 22-38
22.5.2.7
AC Characteristics ............................................................................................... 22-39
22.5.3
Limitations ................................................................................................................... 22-41
22.6
Application Note ............................................................................................................. 22-42
22.6.1.1
Channel to pin mapping ....................................................................................... 22-42
22.6.1.2
Pin mapping RSDS .............................................................................................. 22-42
22.6.1.3
Pin mapping TTL ................................................................................................. 22-42
22.6.2
Example Control Flow ................................................................................................... 22-1
23
Run-Length Decompression (RLD) ......................................................................................... 23-1
23.1
Position of Block in whole LSI .......................................................................................... 23-1
23.1.1
Data Flow in the LSI ..................................................................................................... 23-1
23.2
Overview ........................................................................................................................... 23-2
23.3
Feature List ....................................................................................................................... 23-2
23.3.1
References .................................................................................................................... 23-2
23.3.2
Integration and Application Hints .................................................................................. 23-2
23.3.2.1
Usage of RLD with Jade-D .................................................................................... 23-2
23.4
Communication Protocols (Timing Diagrams) .................................................................. 23-2
23.4.1
Result Interface ............................................................................................................. 23-2
23.4.2
Configuration Bus Interface .......................................................................................... 23-2
23.4.3
Interrupt ......................................................................................................................... 23-2
23.5
Data Formats .................................................................................................................... 23-3
23.5.1.1
Input Data Format .................................................................................................. 23-3
23.5.1.2
Output Data Format ............................................................................................... 23-4
23.6
Software Interface ............................................................................................................ 23-4
23.6.1
Format of Register Description ..................................................................................... 23-4
23.6.2
Global Address ............................................................................................................. 23-5
23.6.3
Register Summary ........................................................................................................ 23-5
23.6.4
Register Description ..................................................................................................... 23-6
23.7
Processing Mode .............................................................................................................. 23-9
23.7.1
Processing Flow............................................................................................................ 23-9
23.7.2
Processing Algorithm .................................................................................................... 23-9
23.7.2.1
Processing Modes ................................................................................................. 23-9
23.8
Control Flow ..................................................................................................................... 23-9
23.8.1
Example Control Flow ................................................................................................... 23-9
23.9
Limitations ...................................................................................................................... 23-10
23.9.1
AHBMTransferWidth Setup ........................................................................................ 23-10
24
General-Purpose Input/Output Port (GPIO) ............................................................................ 24-1
24.1
Outline .............................................................................................................................. 24-1
24.2
Feature ............................................................................................................................. 24-1
24.3
Block diagram ................................................................................................................... 24-1
24.4
Supply clock ..................................................................................................................... 24-2
24.5
Limitations ........................................................................................................................ 24-2
24.6
Register ............................................................................................................................ 24-3
24.6.1
Register list ................................................................................................................... 24-3
24.6.2
Port data register 0-2 (GPDR0-2) ................................................................................. 24-5
24.6.3
Data direction register 0-2 (GPDDR0-2) ....................................................................... 24-7
24.7
Operation .......................................................................................................................... 24-9
24.7.1
Direction control ............................................................................................................ 24-9
24.7.2
Data transfer ................................................................................................................. 24-9
25
Pulse Width Modulator (PWM) ................................................................................................ 25-1
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