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MB86R02 'Jade-D' Hardware Manual V1.64
DCM2 (Display Control Mode 2)
Register
DisplayBaseAddress + 0x104
address
Bit number
31 30 29 28 27 26
Bit field name
R/W
Initial value
Bit0
RUM (Register Update Mode)
The mode reflects the register value synchronizing with vertical synchronization is
selected.
0:
1:
Bit1
RUF (Register Update Flag)
The value is scheduled to be updated in the next vertical sync by writing 1 to this flag.
When the update is completed, it becomes 0.
0:
1:
----
17 16 15 14 13 12 11 10 9 8 7 6 5
Reserve
R0
0
The register update is done in internal control circuit real time. The display is
disturbed if an update occurs in the display period.
The value of the register propagates through the internal control circuit in sync
with vertical synchronization. This syncing is controlled using the RUF flag.
Initial or update end
Vertical synchronous waiting
4
3
2
1
0
Reserv
Reserv
RUF
RUM
R0
R0
RW
RW
0
0
0
0
18-69
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