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MB86R02 'Jade-D' Hardware Manual V1.64
13.6.2 DRAM initialization control register (DRIC)
DRIC register is used to initialize DRAM; in addition, it controls initialization mode setting, issue
of initialization command, and others.
Address
Bit
15
14
13
Name
DRINI CKEN
-
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
1
0
X
Bit field
No.
Name
15
DRINI
14
CKEN
13-4
(Reserved)
3
REFBSY
2
DDRBSY
1
CMDRDY
12
11
10
9
-
-
-
-
X
X
X
X
This sets DRAM initialization operation mode.
0
Normal operation
1
Initialization mode (Initial value)
When initialization is completed, this bit becomes 0.
Only when DRINI bit is 1, CKEN and DRCMD bits of this register, and DRAM
initialization command register [1]/[2] become valid. When this bit is 0, these registers
and bits are don't care.
Note:
•
Data access and auto. refresh to DRAM are not performed in the initialization
operation mode.
•
Only when there is no access request to DDR, DRINI bit can be changed to 0 → 1.
The access request to DDR is able to be judged by DDRBSY (bit 2.)
•
When DRINI bit is "1", do not access to data from AXI. When data access is
requested in the state of DRINI = 1, DDR2 controller may keep occupying the AXI
bus. Moreover, the data requested from AXI may be destroyed.
This is CKE control signal to DDR.
Normal operation (DRINI = 0): CKE output always becomes "1"
Initialization mode (DRINI = 1): CKE output becomes "1"
Reserved bits.
Write access is ignored.
This bit indicates refresh cycle to DDR.
0
It is not refresh cycle
1
It is refresh cycle
This bit indicates status that data access is requested to DDR.
0
Neither command request to DDR nor access to DDR occurs
1
Command request to DDR or access operation to DDR occurs (busy)
This bit indicates DRAM command is ready. It also shows whether "1" is able to be
written to DRCMD bit (writing command bit to DRAM.)
0
1 cannot be written to DRCMD (bit 0)
1
1 can be written to DRCMD
This bit indicates valid value for only at DRINI = 1.
CMDRDY bit becomes "1" in the following cases:
•
Between writing "1" to DRCMD (bit 0) to completion of the command.
•
When DRINI bit is changed to 0 → 1 without reset, accessing to DRAM is not
completed.
F300_0000
+ 00
H
H
8
7
6
5
-
-
-
-
X
X
X
X
Description
4
3
2
1
-
REFBSY DDRBSY CMDRDY DRCMD
R
R
R
W
X
X
X
X
13-5
0
X
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