Fujitsu MB86R02 Jade-D Hardware Manual page 745

MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
No. Name
7-6 (Reserved) Reserved bits.
The write access is ignored. The read value of these bits is always "0".
5-4 RPTMR[1:0] This is packet reception completion timer setting bit which sets time-out value of the internal
reception completion timer.
Reception FIFO is not empty and number of its data is smaller than threshold value: The
timer always counts up
Reception FIFO is empty or the data value is threshold value or more: The timer is cleared.
When the timer becomes time-out, EOPI bit of STATUS register is set to "1".
The timer becomes "00" by software reset.
3-0 RFTH[3:0] Threshold value of reception FIFO is set.
Number of reception word written to reception FIFO is threshold value or more and RXFIM is
"0": Interrupt to CPU occurs
Number of reception word written to reception FIFO is threshold value or more and RXFDM is
"0": DMA is requested to DMAC
RFTH is set according to the following expressions.
RFTH = Reception FIFO threshold – 1
27-18
00 0 (the timer is not in operation)
01 54000 AHB clock cycles
10 108000 AHB clock cycles
11 216000 AHB clock cycles
Description