Fujitsu MB86R02 Jade-D Hardware Manual page 226

MB86R02 'Jade-D' Hardware Manual V1.64
Table 11-3 Relation of byte lane at big endian
Endian Access MPX_MODE_
(BIGEND) size 1[1:0]
16 bit
( ≠ 2'b01)
Word
32 bit
(=2'b01)
16 bit
( ≠ 2'b01)
Half-Word
Big 32 bit
(=1'b1) (=2'b01)
16 bit
( ≠ 2'b01)
Byte
32 bit
(=2'b01)
H*DATA: HWDATA or HRDATA is internal signals
Target width Internal bus Enabled byte lane Corresponding internal
(WDTH) address
MEM_ED[15:8]
MEM_ED[15:8]
8bit 0
MEM_ED[15:8]
MEM_ED[15:8]
MEM_ED[15:0]
16bit 0
MEM_ED[15:0]
32bit(prohibited) -
MEM_ED[15:8]
MEM_ED[15:8]
8bit 0
MEM_ED[15:8]
MEM_ED[15:8]
MEM_ED[15:0]
16bit 0
MEM_ED[15:0]
32bit 0 MEM_ED[31:0]
0 MEM_ED[15:8]
MEM_ED[15:8]
8bit
2 MEM_ED[15:8]
MEM_ED[15:8]
0 MEM_ED[15:0]
16bit
2 MEM_ED[15:0]
32bit(prohibited) -
0 MEM_ED[15:8]
MEM_ED[15:8]
8bit
2 MEM_ED[15:8]
MEM_ED[15:8]
0 MEM_ED[15:0]
16bit
2 MEM_ED[15:0]
0 MEM_ED[31:16]
32bit
2 MEM_ED[15:0]
0 MEM_ED[15:8]
1 MEM_ED[15:8]
8bit
2 MEM_ED[15:8]
3 MEM_ED[15:8]
0 MEM_ED[15:8]
1 MEM_ED[7:0]
16bit
2 MEM_ED[15:8]
3 MEM_ED[7:0]
32bit(prohibited) -
0 MEM_ED[15:8]
1 MEM_ED[15:8]
8bit
2 MEM_ED[15:8]
3 MEM_ED[15:8]
0 MEM_ED[15:8]
1 MEM_ED[7:0]
16bit
2 MEM_ED[15:8]
3 MEM_ED[7:0]
0 MEM_ED[31:24]
1 MEM_ED[23:16]
32bit
2 MEM_ED[15:8]
3 MEM_ED[7:0]
bus data
st
1 : H*DATA[31:24]
nd
2 : H*DATA[23:16]
rd
3 : H*DATA[15:8]
th
4 : H*DATA[7:0]
st
1 : H*DATA[31:16]
nd
2 : H*DATA[15:0]
- -
st
1 : H*DATA[31:24]
nd
2 : H*DATA[23:16]
rd
3 : H*DATA[15:8]
th
4 : H*DATA[7:0]
st
1 : H*DATA[31:16]
nd
2 : H*DATA[15:0]
H*DATA[31:0]
st
1 : H*DATA[31:24]
nd
2 : H*DATA[23:16]
st
1 : H*DATA[15:8]
nd
2 : H*DATA[7:0]
H*DATA[31:16]
H*DATA[15:0]
- -
st
1 : H*DATA[31:24]
nd
2 : H*DATA[23:16]
st
1 : H*DATA[15:8]
nd
2 : H*DATA[7:0]
H*DATA[31:16]
H*DATA[15:0]
H*DATA[31:16]
H*DATA[15:0]
H*DATA[31:24]
H*DATA[23:16]
H*DATA[15:8]
H*DATA[7:0]
H*DATA[31:24]
H*DATA[23:16]
H*DATA[15:8]
H*DATA[7:0]
- -
H*DATA[31:24]
H*DATA[23:16]
H*DATA[15:8]
H*DATA[7:0]
H*DATA[31:24]
H*DATA[23:16]
H*DATA[15:8]
H*DATA[7:0]
H*DATA[31:24]
H*DATA[23:16]
H*DATA[15:8]
H*DATA[7:0]
MEM_XWR MEM_XWR MEM_EA[1]
[3:2] [1:0]
0
01
0
not active
1
01
1
0
not active 00
1
- - -
0
01
0
not active
1
01
1
0
not active 00
1
00 00 0
01 0
not active
0
01 1
not active
1
not active 00 0
not active 00 1
- - -
01 0
not active
0
01 1
not active
1
not active 00 0
not active 00 1
00 11 0
11 00 0
not active 01 0
not active 01 0
not active 01 1
not active 01 1
not active 01 0
not active 10 0
not active 01 1
not active 10 1
- - -
not active 01 0
not active 01 0
not active 01 1
not active 01 1
not active 01 0
not active 10 0
not active 01 1
not active 10 1
01 11 0
10 11 0
11 01 0
11 10 0
11-19