Clock Generation - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
5.5.2

Clock Generation

The MB86R02 'Jade-D' device has several clock domains. The pixel clock domain operates with a
modulated clock in order to reduce electromagnetic interference in the display controller and display
output modules. A second domain operates with a non-modulated clock in order to communicate with
the automotive network.
Each clock can be seperately disabled (see registers CRHA, CRHB, CRPA, CRPB, CRAM). Please
be aware that each clock is enabled after a reset. For power saving reasons, clocks for non-active
modules should be disabled.
External pin
XTAL0
REF
OSC
XTAL1
External pin
CRG
configuration
configuration
Feedback divider N
Pre divider P
SELXCK
Main
Pre PLL
m
DIV (up to
u
x
666
1/p
MHz)
APIX
PLL
CDR
500MHz
CDR
250MHz
Figure 5-3 Overview of Clock Structure PLL's
configuration
Bypass, enable
Rate, etc...
SSCG
400..7
1
00MH
0
z
SELM
SELMCCLK
1
DIV
0
1/2
configuration
Clock gating
APIX core clock 0 & 1
Mux are spikefree
PLLCLKM
Display Reference clock
Modulated
CCLK
0
Not Modulated
System clock
1
PLLBYPASS
5-7