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MB86R02 'Jade-D' Hardware Manual V1.64
31-5
–
4-0
DCGATE[4:0]
5.1.13.
Clock Selector control register (CSEL)
COMPLETE REGISTER is reserved
This register controls clock multiplexers.
Address
Bit
31
30
29
Name
–
–
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
Bit
15
14
13
Name
R/W
R1
R1
R1
Initial value
0
0
0
Bit field
No.
Name
31-16
–
15-5
Reserved
4
Reserved
3
Reserved
2
SELM
1
(Not available
in ES1)
SELMCCLK
0
Reserved
Unused bits.
Write access is ignored, and read value of these bits is undefined.
DCLK clock gate control
These bits control DCLK clock gate (Pixelclock).
DCGATE[n]
0
DCCLKn stops
1
DCLKn does not stop (initial value)
DCLK0: CLUT, DITH Pixelclock
DCLK1: TCON Pixelclock (only register CRDP0)
DCLK2: TCON Bitclock (only register CRDP0)
DCLK3: SIG Pixelclock
DCLK4: APIX transmitter Pixelclock
Note: for register CRDP1 DCGATE[2:1] is reserved (no TCON at DPERI1)
Base address + 34
28
27
26
25
–
–
–
–
X
X
X
X
12
11
10
9
Res
R1
R1
R1
R1
0
0
0
0
Unused bits.
The write access is ignored, and read value of these bits is undefined.
Reserved bits.
Write access is ignored, and read value of these bits is always "1".
Reserved bits.
Write access is ignored, and read value of these bits is always "1".
Reserved bits.
Write access is ignored, and read value of these bits is always "1".
Clock selection for PLLCLKM (used for dotclock generation)
0
Non-modulated clock, bypass of SSCG (initial value)
1
modulated clock
Clock source selection for CCLK (system master clock)
0
Non-modulated clock (initial value)
1
modulated clock
This modulated system master clock has impact on all peripherals including e.g. CAN,
MLB. It must be checked by the relevant application whether all peripherals can be
operated with modulated clock. Please adapt the modulation range accordingly.
Reserved bits.
Write access is ignored, and read value of these bits is always "0".
Description
H
24
23
22
21
–
–
–
–
X
X
X
X
8
7
6
5
RES
RES
RES
RES
R1
R1
R1
R1
R/W R/W R/W R/W R/W
0
0
0
0
Description
20
19
18
17
–
–
–
–
X
X
X
X
4
3
2
1
RES
SELM
RES
RES
0
0
0
0
5-33
16
–
X
0
0
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