Stop And Return From Sleep Mode - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

9.6.5 Stop and return from sleep mode

The instruction of the return from the stop and sleep mode can be given to the clock controller by FIQ
from the macro or issuing the IRQ interrupt.
The return signal from the stop and the sleep mode asserted to the ARM clock controller is generated
with the OR of the FIQ factor asserted from IRQ factor and other macros that are higher than the
interrupt level set depending on the ILM register (logical add). (Refer to Figure 9-1)
It becomes impossible the return from the stop and sleep mode it therefore when the following
interrupt factors occur.
Note of return by FIQ source
The factor occurs in the macro even if the FIQ factor is asserted and the return doesn't occur when
masking alleged. This is because the interrupt is not transmitted by the interrupt controller.
Note of return by IRQ factor
The factor occurs in the macro even if the FIQ factor is asserted and the return doesn't occur when
masking alleged. This is because the interrupt is not transmitted by the interrupt controller.
The IRQ factor lowers more than the interrupt level set depending on the ILM register.
When you do neither the stop by the FIQ factor nor the return from sleep mode
•
The interrupt of the mask by the macro.
•
Set to become lower to the ILM register the level of the corresponding IRQ interrupt.
•
Do not to transmit the interrupt to the interrupt controller for the DMA transfer in sleep mode,
and not to return from sleep mode.
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