Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
6 Spread Spectrum Clock Generator (SSCG)
6.1 Position of Block in whole LSI
The SSCG unit is the heart of the digital system and provides a modulated clock signal for reduced EMI. It is
therefore located in the clock generation, control and distribution modules.
PLL
6.2
Features
6.2.1 Functional
• Input Frequency Range :
• Modulation Period:
• Modulation Period Delta
• Modulation type:
• Modulation peak:
• Modulation shape:
• Frequency offset
• Maskable Interrupt generation:
6.2.2 Limitations
Do not modify any SSCG registers during operation of the SSCG unit
Please stop the SSCG by changing SSCG_EN =0 if you need to modify the SSCG registers
Config-Bus
SSCG
Modulated clock
Non modulated clock
Figure 6-1 Location of the SSCG unit in the GDC
switchable 400MHz – 700MHz
variable from 1 / 1.048.320 to 1 / 256 of PLL clock
continuously from 0 to 12.5% of the modulation period
non-modulated
downspread,
center spread (default)
Default ±1.0%
Center spread:
-1.56% to +1.56%
Downspread:
0 to 1.56%
Upspread:
0 to +1.56% (not used!)
triangle, dual triangle
-1.56% to +1.56%, default 0
Generate an interrupt on an illegal configuration setting
CLOCK /
RESET
Distribution
.
clk0
clkn
rst0_n
rstn_n
6-1
Advertisement
Table of Contents
