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MB86R02 'Jade-D' Hardware Manual V1.64
25.7.2
PWMx base clock register (PWMxBCR)
This register is to set base clock of PWM cycle.
Address
Bit
31
30
29
Name
R/W
R
R
R
Initial value
0
0
0
Bit
15
14
13
Name
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
0
0
0
Bit field
No.
Name
31-16
(Reserved)
15-0
BCR
ch0：FFF4_1000 + 00
ch1：FFF4_1100 + 00
ch2：FFF4_6000 + 00
ch3：FFF4_6100 + 00
ch4：FFF4_7000 + 00
ch5：FFF4_7100 + 00
ch6：FFF4_8000 + 00
ch7：FFF4_8100 + 00
28
27
26
25
R
R
R
R
0
0
0
0
12
11
10
9
0
0
0
0
Reserved bits.
Write access is ignored. The read value of these bits is always "0".
Sets the base clock of the PWM cycle.
BCR[15:0]
0 APBCLK
0
1
1 APBCLK
|
|
65535
65535 APBCLK
H
H
H
H
H
H
H
H
24
23
22
21
(Reserved)
R
R
R
R
0
0
0
0
8
7
6
5
BCR[15:0]
0
0
0
0
Description
Base clock
(Setting
prohibited)
20
19
18
17
R
R
R
R
0
0
0
0
4
3
2
1
0
0
0
0
25-5
16
R
0
0
0
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