Memory Controller Signal Timing; Ac Characteristics - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

34.5 AC Characteristics

In this chapter, the AC timing of external ports is described.
34.5.1

Memory Controller Signal Timing

Table 34-17 Memory Controller AC Timing
Signal Name Symbol
MEM_XCS0
t
MEM_XCS2
cso
MEM_XCS4
t
MEM_EA[24:1]
ao
t
do
t
doz
t
dsr
MEM_ED[31:0]
t
dhr
t
dsp
t
dhp
t
MEM_XRD
rdo
t
MEM_XWR[3:0]
wro
Standard clock of output delay is internal clock
Standard clock of MEM_RDY is internal clock
Load capacitance = 30pF
34-16
Description
Chip Select delay time
Address delay time
Data output delay time
Data output HiZ time
SRAM/NOR Flash data setup time
SRAM/NOR Flash data hold time
NOR Flash page Read data setup time
NOR Flash page Read data hold time
XRD delay time
XWR delay time
Value
Min Typ Max
– – 11
– – 11
– – 11
– – 12
18 – –
0 – –
18 – –
0 – –
– – 11
– – 11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns