Dma Controller (Dmac); Outline; Feature - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

15 DMA Controller (DMAC)

This chapter describes the functionality and operation of the DMA Controller.

The DMAC is an 8-channel DMA controller.

DMAC in MB86R02 has following features:

• Compliant with AMBA v2.0

• 8 DMA channels

• DMA trigger

• External transfer request (2 channels for external DMA request and 2 channels for I2S

transmission/reception DMA requests are available). Note that although I2S is an

internal peripheral, its DMA requests are handled as external.

• Peripheral transfer request (12 types of UART transmission/reception DMA request

selectable per channel)

• Software request (start-up by register write)

• Beat transfer

16-word FIFO shared by all channels

Supports INCR, INCR 4/8/16, and WRAP 4/8/16.

• Transfer modes:

• Block transfer (I2S: check 'Limitations with I2S' section)

• Burst transfer (not to I2S!)

• Demand transfer (not to I2S!)

• Programmable 4 bit block register and 16 bit count register

• Supports 8, 16, and 32 bit transfer widths

• Supports increment and fixed addressing to source and destination

• Reload count, source address and destination address register

• Issues interrupts on errors and completion

• Displays end code of DMA transfer

• Supports source and destination protection

• Hardware support for fixed priority and rotation priority

In fixed priority mode, channel 0 has the highest and channel 7 has the lowest priority