Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
L5OA0 (L5 layer Origin Address 0)
Register
DisplayBaseAddress + 0x8C
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
Initial value
This register sets the origin address of the logic frame of the L5 layer in frame 0. Since lower 4 bits
are fixed to "0", this address is 16-byte aligned.
L5DA0 (L5 layer Display Address 0)
Register
DisplayBaseAddress + 0x90
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
Initial value
This register sets the origin address of the L5 layer in frame 0. For the direct color mode (16
bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned.
L5OA1 (L5 layer Origin Address 1)
Register
DisplayBaseAddress + 0x94
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
Initial value
This register sets the origin address of the logic frame of the L5 layer in frame 1. Since lower 4-bits
are fixed to "0", this address is 16-byte aligned.
L5OA1 (L5 layer Display Address 1)
Register
DisplayBaseAddress + 0x98
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
Initial value
This register sets the origin address of the L5 layer in frame 1. For the direct color mode (16
bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned.
L5DX (L5 layer Display position X)
Register
DisplayBaseAddress + 0x9C
address
Bit number
15
Bit field name
Reserved
R/W
Initial value
This register sets the display starting position (X coordinates) of the L5 layer on the basis of the
origin of the logic frame in pixels.
18-94
14
13
12
11
10
R0
0
BROA0
RW
X
L5DA0
RW
X
L5OA1
RW
X
L5DA1
RW
X
9
8
7
6
5
L5DX
RW
X
RW0
RW0
4
3
2
1
0
Advertisement
Table of Contents
