Basic Reception Operation - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

28.7.5 Basic reception operation

M ar k st at e

After detecting received start bit ("L" level) from serial input (SIN) pin, the bit receiving next is

regarded as start bit of reception data.

Then, received data is sampled with reception clock, and stop bit is detected after receiving data

bit and parity bit. When transmission error occurs during that time, its factor (break detection,

flaming error, parity error, and overrunning error) is applied to each data in FIFO, and the status is

maintained. Status can be confirmed by CPU at the first data of FIFO.

When reception data ready interrupt is permitted, interrupt (INTR) pin becomes "H" and interrupt

occurs by reaching the data in reception FIFO to the trigger level. This interrupt is released when

the data in the FIFO becomes less than the trigger level, and interrupt (INTR) pin becomes "L".

XRXRDY is data ready signal that shows possible reception to DMA controller at using the

controller. Single transfer mode is supported when bit 3 of the FCR register is "0" and the

demand transfer mode is supported when the bit is "1".

When transmission baud rate of the other party and baud rate used by macro are within the

reception baud rate permissible error range, data is able to be received properly. Out of the

range causes reception error. Baud rate permissible error range that macro permits is as

104.1% > Macro baud rate (100%) > 95.3%

After reset (MR = 1), the time reaching to enable detection of start bit is 1/4 bit after DLL and DLM

Even if start bit (SIN=0) is received during this period, normal start bit detection is not performed.

1 char act er

Thi s i s exam pl e of t he case, dat a bi t l engt h i s 6 bi t and st op bi t l engt h i s 2 bi t , and par i t y

Figure 28-6 Basic reception operation

Par i t y bi t