Fujitsu MB86R02 Jade-D Hardware Manual page 29

MB86R02 'Jade-D' Hardware Manual V1.64
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AHB1: Each bus master of the AHB bus (e.g. the CPU core and the DMA controller)
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AHB3: The connection to the CPU core
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HBUS: The HOST interface of the GDC
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DRAW & GEO: DRAW, the drawing engine (2D/3D drawing) and GEO, the geometry
engine of the GDC
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MBUS: DISP (display controller) and CAP (video capture) of the GDC
AHB1 bus (32 bit/83 MHz)
The following resources are connected to the AHB1 bus:
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GDC: GDC registers
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AHB2AXI: AXI port for external main memory access
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CCPB: Encrypted ROM decoding block
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External BUS I/F: External bus interface (connected through CCPB)
SRAM: General purpose internal SRAM 32KB × 2
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DMAC: General purpose DMA × 8ch. This operates as a bus master during data transfer
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TIC (Test Interface Controller)
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Boot ROM: Built-in boot ROM (32KB)
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RLD (Run-Length De-compression unit). Used e.g. for fast logo display
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MLB: MediaLB controller
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SDMC: SD memory controller
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Host SPI (Serial Peripheral Interface) SPI is a serial interface for synchronous
communication
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APIX Remote Handler (RX/TX channels can act as Master or Slave)
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AHB2 bus
AHB2 bus (32 bit/83 MHz)
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CCPB: Encrypted ROM decoding block
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DDR2 controller: DDR2 controller registers
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Host SPI (Serial Peripheral Interface) SPI is a serial interface for synchronous
communication
I2S_0: Serial audio controller × 1ch
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APBBRG0/1/2: AHB-APB bridge circuit × 3ch
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AHB1 bus
AHB3 bus (32 bit/166 MHz)
The following resources are connected to the AHB3 bus:
GDC: GDC registers
AHB2AXI: AXI port for external main memory access
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AHB2 bus
APB_TOP_0 (32 bit/41.5 MHz)
This block acts as a bridge between the AHB2 bus (via the APBBRG0 async module) and the
following low-speed peripheral resources:
Interrupt controller (IRC) × 3ch
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External interrupt controller (EXTIRC) x 4ch
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Clock reset generator (CRG)
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SSCG (Spread-spectrum Clock Generator) for reduced EMI
UART (ch0 and ch1) × 2ch
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GPIO x 24ch
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Remap boot controller (RBC)
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