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MB86R02 'Jade-D' Hardware Manual V1.64
Bit
init
Name
:
ial
cfg_dwnBwMode[1]
7
1
cfg_dwnBwMode[0]
6
1
Reserved
5
1
Reserved
4
1
cfg_px_in_ctrl_piggyback[1]
3
1
cfg_px_in_ctrl_piggyback[0]
2
1
cfg_pxdata_width[1]
1
1
cfg_pxdata_width[0]
0
0
Table 17-16 TX config_byte_2
The maximum pixel clock frequencies listed in Table 17-1 are achievable only if pixel
controls are transmitted with even pixels ('cfg_px_in_ctrl_piggyback' = "10").
pixel data bit width
10
12
18
24
Table 17-1, maximum pixel clock frequency with cfg_px_in_ctrl_piggyback[1:0] = "10"
config_byte_2
Description
APIX PHY (Hard IP): selects downstream
bandwidth mode
11: 1000 Mbit/s (Full Bandwidth Mode)
10:
500 Mbit/s (Half Bandwidth Mode)
01:
250 Mbit/s (Low Bandwidth Mode 2)
00:
125 Mbit/s (Low Bandwidth Mode 1)
Do not change
Do not change
APIX PHY (Soft IP): transmission of pixel
controls
00: never
01: unused
10: with even pixels only
11: with every pixel
APIX PHY (Soft IP): bit width of pixel data
00: 10 bits
01: 12 bits
10: 18 bits
11: 24 bits
maximum pixel clock
frequency using
Full Bandwidth
(1 GBit/s) Mode
62.0 MHz
61.0 MHz
42.0 MHz
32.0 MHz
maximum pixel clock
frequency using
Half Bandwidth (500
MBit/s) Mode
31.0 MHz
30.5 MHz
21.0 MHz
16.0 MHz
17-27
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