Fujitsu MB86R02 Jade-D Hardware Manual page 62

MB86R02 'Jade-D' Hardware Manual V1.64
MPX TEST MPX_MODE_5_0
MPX TEST VPD
MPX TEST TESTMODE_3
MPX TEST TESTMODE_2
MPX TEST TESTMODE_1
MPX TEST TESTMODE_0
MPX TEST JTAGSEL
MPX TEST TESTMODE_4
PLL #PLLVDD
PLL #PLLVSS
PWM PWM_O3
PWM PWM_O2
PWM PWM_O1
PWM PWM_O0
SPI(m)0 SPI_DI0
SPI(m)0 SPI_DO0
SPI(m)0 SPI_SS0
SPI(m)0 SPI_SCK0
SPI(m)1 SPI_DI1
SPI(m)1 SPI_DO1
SPI(m)1 SPI_SS1
SPI(m)1 SPI_SCK1
SPI(s)Host HOST_SPI_SCK
SPI(s)Host HOST_SPI_DI
SPI(s)Host HOST_SPI_DO
SPI(s)Host HOST_SPI_SS
SSCG #SSCGVDD
SSCG #SSCGVSS
SYSTEM PLLTDTRST
SYSTEM CLK_SEL
SYSTEM ECLK
SYSTEM CRIPM0
SYSTEM CRIPM1
SYSTEM CRIPM2
SYSTEM CRIPM3
SYSTEM OSC_FILTER
SYSTEM XTAL0
SYSTEM XTAL1
SYSTEM OSC_MODE1
SYSTEM OSC_BIAS0
SYSTEM OSC_BIAS1
1-38
D
U4 I Multiplex Mode Pin
D
AF12 I Multiplex Mode Pin
AE12 D I Test Mode Pin
D Test Mode Pin, In Functional Mode this pin selects the
AD12 I
Endianess: Low: Little endian, High: Big endian
AE15 D I Test Mode Pin, in functional Mode PLLBYPASS
D
AD15 I Test Mode Pin
JTAG Selector (0 = Fujitsu TAP Controller, 1 = ARM Tap
E8 D I
Controller)
D
C6 I Test Mode Pin
PLL Supply: 1,2 Volt / In case it is derived from core supply
E14 A I
a protection by a filter is recommended.
PLL Supply (separated ground plane recommended,
E13 A I
connection via filter to digital ground)
D
AF10 O PWM Output
AE10 D O PWM Output
D
AD10 O PWM Output
D
AC10 O PWM Output
D
AF18 I SPI0 Master Data Input (MISO)
D
AE18 O SPI0 Master Data Output (MOSI)
AD18 D O SPI0 Master Slave Select
D
AC18 O SPI0 Master serial clock
AF19 D I SPI1 Master Data Input (MISO)
D
AE19 O SPI1 Master Data Output (MOSI)
D
AD19 O SPI1 Master Slave Select
AC19 D O SPI1 Master serial clock
D
AF11 I HOST SPI Clock
AE11 D I HOST SPI Data Input (MOSI)
D
AD11 O HOST SPI Data Output (MISO)
D
AC11 I HOST SPI Slave Select
A I SSCG Supply: 1,2 Volt / In case it is derived from core
C14
supply a protection by a filter is recommended.
A I SSCG Supply (separated ground plane recommended,
D14
connection via filter to digital ground)
D Test pin
E4 I
Pull up the pin to VDDE, via high resistance
D
K2 I Select Pin for emb. Crystal CLK or ECLK
D
A16 I External Clock Source (selected by CLK_SEL)
D
A15 I PLLMODE setting
B15 D I PLLMODE setting
D
C15 I PLLMODE setting
D
B14 I PLLMODE setting
D
C12 I characteristic of post-oscillator filter
A
A11 I Crystal reference
B11 A I Crystal reference
D
B8 I oscillator mode 1
D
C8 I Oscillator bias level 0
D
D8 I Oscillator bias level 1
STDIO
-
- PD
- STDIO
STDIO
-
- STDIO
STDIO
-
STDIO
-
STDIO
-
STDIO
L
STDIO
L
L PD
- PD
L PD
- PD
STDIO
HiZ
STDIO
-
- STDIO
STDIO
-
HiZ STDIO
STDIO
-
STDIO
L
L STDIO
HiZ PU *
HiZ PU *
L STDIO
HiZ PU *
STDIO
L
STDIO
L
- PU *
STDIO
-
STDIO
-
STDIO
-
- STDIO
STDIO
-
STDIO
-
STDIO
-
STDIO
L
L STDIO
STDIO
-
STDIO
-
STDIO
-