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MB86R02 'Jade-D' Hardware Manual V1.64
IO Module Pad 0 Control
Bit 20 -
NChanSel0
19
Channel selection for N-Pin of Pad i=0 TTL: 00b=channel(i*2+1), 01b=channel(i*2), 10b=clk, 11b=const0 (TTL mode only)
Bit 18 -
ChanSel0
17
Channel selection for Pad i=0: for RSDS: 00b=channel i, 01b=reserved, 10b=clk, 11b=const0, for TTL: 00b=channel i*2, 01b=INV
(from inversion control function), 10b=clk, 11b=const0
Bit 14
NDelay0
N-pin Padcell 0 delay: 0b=no delay, 1b= half bit clock cycle delay (TTL-mode only)
Bit 13
Delay0
Pad 0 delay: 0b=no delay, 1b= half bit clock cycle delay
Bit 7
InOut0
output enable control, 0b=input enabled, 1b=output enabled
Bit 6
NPolarity0
N-pin of Padcell 0 drive polarity: TTL: 0=normal, 1=inverted; RSDS: no effect
Bit 5
Polarity0
Pad 0 drive polarity: TTL :0=normal, 1=inverted; RSDS: 1=normal, 0=inverted
Bit 4
Mode0
Pad 0 drive mode: 0b=differential, 1b=TTL
Bit 1 - 0
Boost0
Boost factor for drive current: x0b=2mA, x1b=4mA (only boost[0] has effect)
DIR_PIN1_CTRL
Register
BaseAddress + 538
H
address
Bit
31 30 29 28 27 26 25 24 23 22 21 20
number
Field
name
R/W
Reset
value
IO Module Pad 1 Control
Bit 20 -
NChanSel1
19
Channel selection for N-Pin of Pad i=1 TTL: 00b=channel(i*2+1), 01b=channel(i*2), 10b=clk, 11b=const0 (TTL mode only)
Bit 18 -
ChanSel1
17
Channel selection for Pad i=1: for RSDS: 00b=channel i, 01b=channel(i-1), 10b=clk, 11b=const0, for TTL : 00b=channel i*2,
01b=channel i*2-1, 10b=clk, 11b=const0
Bit 14
NDelay1
N-pin Padcell 1 delay: 0b=no delay, 1b= half bitclock cycle delay (TTL-mode only)
Bit 13
Delay1
Pad 1 delay: 0b=no delay, 1b= half bit clock cycle delay
Bit 7
InOut1
output enable control, 0b=input enabled, 1b=output enabled
Bit 6
NPolarity1
N-pin of Padcell 1 drive polarity: TTL: 0=normal, 1=inverted; RSDS: no effect
Bit 5
Polarity1
Pad 1 drive polarity: TTL: 0=normal, 1=inverted; RSDS: 1=normal, 0=inverted
Bit 4
Mode1
Pad 1 drive mode: 0b=differential, 1b=TTL
Bit 1 - 0
Boost1
Boost factor for drive current: x0b=2mA, x1b=4mA (only boost[0] has effect)
DIR_PIN2_CTRL
Register
BaseAddress + 53C
H
address
Bit
31 30 29 28 27 26 25 24 23 22 21 20
number
Field
name
R/W
Reset
value
IO Module Pad 2 Control
Bit 20 -
NChanSel2
19
Channel selection for N-Pin of Pad i=2 TTL: 00b=channel(i*2+1), 01b=channel(i*2), 10b=clk, 11b=const0 (TTL mode only)
Bit 18 -
ChanSel2
17
Channel selection for Pad i=2 for RSDS: 00b=channel i, 01b=channel(i-1), 10b=clk, 11b=const0, for TTL: 00b=channel i*2,
01b=channel i*2-1, 10b=clk, 1b=const0
Bit 14
NDelay2
N-pin Padcell 2 delay: 0b=no delay, 1b= half bit clock cycle delay (TTL-mode only)
Bit 13
Delay2
Pad 2 delay: 0b=no delay, 1b= half bit clock cycle delay
Bit 7
InOut2
output enable control, 0b=input enabled, 1b=output enabled
Bit 6
NPolarity2
N-pin of Padcell 2 drive polarity: TTL: 0=normal, 1=inverted; RSDS: no effect
19
18
17 16 15
14
NChanSel1 ChanSel1
NDelay1 Delay1
RW
RW
RW
0
0
0
H
H
H
19
18
17 16 15
14
NChanSel2 ChanSel2
NDelay2 Delay2
RW
RW
RW
0
0
0
H
H
H
13
12 11 10 9 8
7
6
InOut1 NPolarity1 Polarity1 Mode1
RW
RW
RW
0
0
0
H
H
H
13
12 11 10 9 8
7
6
InOut2 NPolarity2 Polarity2 Mode2
RW
RW
RW
0
0
0
H
H
H
5
4
3 2 1
0
Boost1
RW
RW
RW
0
1
0
H
H
H
5
4
3 2 1
0
Boost2
RW
RW
RW
0
1
0
H
H
H
22-23
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