Serial Audio Interface (I2S); Outline; Features - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

27 Serial Audio Interface (I2S)

This chapter describes function and operation of serial audio interface (hereafter called, I2S.)

MB86R02 incorporates a one channel audio I/O interface in I2S format.

I2S stands for the Inter-IC Sound Bus by Philips Semiconductors (now NXP).

I2S interface in MB86R02 has following features:

• Selecting master/slave operations by programmable

• Supporting state of transmission only, reception only, and simultaneous

transmission/reception

• Selecting 1 sub frame and 2 sub frame constructions

• Setting up to 32 channels to each sub frame

• Individually setting number of channel in each sub frame

• Individually setting channel length of each sub frame (number channel bit)

• Individually setting word length in channel of each sub frame

• Setting valid/invalid of each channel in each sub frame (Note 1)

• Setting word length from 7 to 32 bit

• Programming frequency of frame synchronous signal

• Setting up to 3071 bit in 1 frame

• Programming width of frame synchronous signal (1 bit or 1 channel length)

• Programming phase of frame synchronous signal (0 bits or 1 bit delay)

• Setting polarity of frame synchronous signal

• Setting polarity of serial bit clock

• Programming sampling point of received data

• Selecting clock frequency dividing source of serial bit clock in the master mode (internal and

external clock.)

• Setting clock frequency dividing ratio in the master mode

Frequency of I2S_SCLK = frequency of AHB clock (or external clock)/2 × CKRT[5:0]

Frequency dividing ratio is settable within 0 – 126 in multiple of 2 (when the ratio is 0,

frequency dividing source is by-passed)

• Data transfer to system memory by DMA (block transfer only, refer to the DMA chapter),

interrupt, and polling

Data is not sent or received to invalid channels