Fujitsu MB86R02 Jade-D Hardware Manual page 287

MB86R02 'Jade-D' Hardware Manual V1.64
Timing chart
Figure 15-5 shows a burst transfer timing chart.
External trigger
DREQ
DACK
DEOP
DSTP
Software trigger
0x00
DMACA[31:24]
HBUSREQ
HGRANT
HCLK
HMASTER CPU
HTRANS
HADDR
HWRITE
Control
HWDATA
HRDATA
HREADY
HRESP
DMACA[19:16] 0x0
BC
DMACA[15:0] 0x0
TC
Figure 15-5 Burst transmission (for BC = 0x1 and TC = 0x1)
15-24
0xA0
HDMAC
N N N
N N
SA DA SA DA SA DA
Data Data
Data Data
OK
0x1 0x0
0x1
N I
N N
SA DA
Data
Data
Data Data
0x1
0x00
CPU
0x0
0x0