Reset/Standby Control Register (Crsr) - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

Reset/Standby control register (CRSR)

This register controls reset and standby.

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value

Initial value

Unused bits.

Write access is ignored, and read value of these bits is undefined.

Reserved bits.

Write access is ignored, and read value of these bits is always "0".

Stop mode enable

This bit stops all bus clock operations in the standby mode.

Bus clock operation in the standby mode does not stop (initial value)

All bus clock operations in the standby mode are stopped

Note: clocks are not stopped immediately

Note: When changing state to stop mode, write "1" to PLLBYPASS bit of CRPR.

Reserved bits.

Write access is ignored, and read value of these bits is always "0".

Reserved bit.

Always write "0" to write access.

nSRST monitoring

This bit monitors nSRST reset from ICE.

nSRST is not asserted

nSRST is asserted

Initial value of this bit is undefined, and writing "0" is ignored.

When nSRST occurs, this bit is set to "1".

Software reset monitoring

This bit monitors software reset.

Software reset is not asserted

Software reset is asserted

Initial value of this bit is undefined, and writing "0" is ignored.

When software reset occurs, this bit is set to "1".

Software reset request

This bit asserts software reset.

Software reset is not requested (initial value)

Software reset is requested

Writing 0 is ignored, and this bit is cleared with reset signal.

R0 R/W0 R/W0 R/W0 R/W1 R/W