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MB86R02 'Jade-D' Hardware Manual V1.64
MDR4 (Mode Register for BLT)
Register
DrawBaseAddress + 430
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
Initial value
This register controls the BLT mode.
Bit 1
TE (Transparent Enable)
Sets transparent mode
0:
1:
Bit 8 to 7
BM (Blend Mode)
Sets blend mode
00
01
10
11
Bit 12 to 9
LOG (Logical operation)
Sets logic operation
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
18-218
H
Not perform transparent processing
Not draw pixels that corresponds to set transparent color in BLT (transparancy
copy)
Note: Set the blend mode (BM) to normal.
Normal (source copy)
Reserved
Drawing with logic operation
Reserved
CLEAR
AND
AND REVERSE
COPY
AND INVERTED
NOP
XOR
OR
NOR
EQUIV
INVERT
OR REVERSE
COPY INVERTED
OR INVERTED
NAND
SET
LOG
BM
RW
RW
0011
00
TE
RW
0
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