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MB86R02 'Jade-D' Hardware Manual V1.64
Note:
Although UART's register length is 8 bit, each register except RFR, TFR, and DLL
should be accessed in 32 bit.
PER, TFR, and DLL are able to be accessed in both 32 bit and 8bit lengths; however,
note that 8 bit length access is different since register address is endian dependent.
Description format of register
Following format is used for description of register's each bit in "28.6.2 Reception FIFO register
(URTxRFR)" to "28.6.11 Divider latch register (URTxDLL&URTxDLM)".
Address
Bit
31
30
29
Name
R/W
Initial value
Bit
15
14
13
Name
R/W
Initial
valu
e
Meaning of item and sign
Address
Address (base address + offset address) of the register
Bit
Bit number of the register
Name
Bit field name of the register
R/W
Attribution of read/write of each bit field
• R0:Read value is always "0"
• R1: Read value is always "1"
• W0: Write value is always "0", and write access of "1" is ignored
• W1: Write value is always "1", and write access of "0" is ignored
• R: Read
• W: Write
Initial value
Each bit field's value after reset
• 0: Value is "0"
• 1: Value is "1"
• X: Value is undefined
Base address + Offset
28
27
26
25
12
11
10
9
24
23
22
21
8
7
6
5
20
19
18
17
4
3
2
1
28-5
16
0
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